FPGA Digital Design Engineer Level 3/4 (AHT) at Northrop Grumman
Los Angeles, CA
$125,300–$234,600from the description
Jul 10, 2026
Los Angeles, CA
Jul 21, 2026
What this job asks for AI summary
An on-site FPGA digital design role supporting a missile program, focused on designing, developing, and verifying high-speed digital hardware across the full product lifecycle. Day-to-day work involves FPGA and ASIC architecture, HDL coding in VHDL or Verilog, DSP algorithm implementation, and collaboration with systems engineering to validate firmware against system requirements. Suits engineers with hands-on FPGA experience using AMD/Xilinx or Intel/Altera platforms and EDA toolchains.
Senior level · 5+ years · Los Angeles-Long Beach-Anaheim, CA · Bachelor's required · Secret clearance · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $112,112 (middle half $73,931–$166,799). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (8)
This posting covers two levels simultaneously: Level 3 (5+ years BS / 3+ years MS) and Level 4 (8+ years BS / 6+ years MS). The salary ranges are also dual: $125,300–$187,900 for Level 3 and $156,400–$234,600 for Level 4. The overall years minimum is set to 5 (the lower gate); the upper gate is 8 years.
FPGA Digital Design is not a standard software-developer role; 15-1299 (Computer Occupations, All Other) is the closest available SOC code. 15-1252 (Software Developers) is listed as the runner-up given the design/verification/firmware coding nature of the work.
The clearance field reflects 'ability to obtain a Secret clearance' as the hard gate for start. An active/current DoD Secret or higher is listed under Preferred Qualifications as a plus, not a hard requirement.
VHDL and Verilog are listed as 'and/or' — either satisfies the requirement; both are emitted as required skills with each as the other's alternative.
AMD/Xilinx and Intel/Altera SoC FPGAs are similarly 'and/or' — emitted as a single required skill with the other as an alternative.
Vivado and Quartus are both listed as required EDA tools (along with QuestaSim); they are emitted as separate required skills since they correspond to different FPGA vendor toolchains that may both be used.
DSP algorithms, MATLAB/Simulink, timing closure, RF design, test equipment, ModelSim/QuestaSim testbenches, VxWorks, and high-speed interfaces (AXI, PCIe, DDR3, etc.) all appear under Preferred Qualifications.
Requires a Secret clearance — the cleared population is a small fraction of this occupation, so the real candidate pool is materially smaller than the estimate below, which does not model clearance.
Read the full posting
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