Senior Principal FPGA Verification Engineer - $15K Sign-On Bonus
BAE Systems · Westminster, CO
$132,962–$226,035from the description
Jul 9, 2026
Westminster, CO
Jul 21, 2026
What this job asks for AI summary
A senior-level role focused on verifying complex FPGA and SoC designs for space and high-reliability electronic systems. Day-to-day work involves leading verification efforts using UVM/OVM methodologies, AMD/Xilinx toolchains, and HDL languages, across R&D and production programs that may include digital signal processing, image processing, and high-speed communication interfaces. Suits an experienced FPGA verification engineer with a strong embedded digital systems background.
Senior level · 8+ years · National · Bachelor's required · Full-time
Advertised as Principal, but the requirements read as Senior.
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (8)
US citizenship is explicitly required by the posting, though no formal security clearance level is stated as a hard gate.
The job title reads 'Senior Principal FPGA Verification Engineer', which is an unusual compound level. Advertised seniority is set to Principal based on the title's highest-level word; however, the actual requirements (8+ years, BS+) are consistent with a Senior-level role on a standard career ladder.
VHDL and Verilog are listed together as a single requirement ('VHDL/Verilog') in the required section; they are captured as a single skill with Verilog as an alternative since either language satisfies the requirement. SystemVerilog is listed separately and is its own distinct skill.
Vivado and Vitis are listed together ('Xilinx Vivado/Vitis') as a single tool requirement; Vitis is captured as an alternative. ModelSim and QuestaSim are similarly paired ('Mentor Modelsim/Questasim').
OVM and UVM are listed together ('OVM/UVM') as a single methodology requirement; OVM is captured as an alternative to UVM.
'Strong design, documentation and implementation of high-speed digital electronics, FPGAs, and embedded processor systems are desired' appears in the required section but uses the word 'desired' — this is a genuine ambiguity. The preferred section repeats this as 'Solid design…' confirming it is aspirational rather than a hard gate; no separate skill was emitted for this general capability.
The $15,000 sign-on bonus is for external hires only and is not reflected in the salary range fields.
SOC classification is a judgment call: FPGA verification engineering sits at the intersection of hardware design and software/HDL development. 15-1252 (Software Developers) is chosen because the primary day-to-day work involves writing and verifying HDL code and testbenches; 15-1299 is noted as a plausible alternative for this specialized hardware-adjacent role.
Read the full posting
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