SoC Verification Engineer
Intel · Hillsboro, OR
$141,910–$200,340from the description
Jul 21, 2026
Hillsboro, OR
Jul 23, 2026
What this job asks for AI summary
This role centers on verifying complex SoC designs before silicon, covering the creation and maintenance of UVM-based testbenches, verification plans at block, subsystem, and SoC levels, and execution of those plans through simulation and emulation. The engineer debugs failures in presilicon environments and works alongside RTL, architecture, and physical design teams. It suits someone with solid hands-on UVM/OVM experience and familiarity with AMBA protocols.
Mid level · 3+ years · Austin, TX · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
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How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $105,337 (middle half $84,324–$133,554). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
The role has two qualifying paths: a Bachelor's degree with 4+ years of SoC verification experience, OR a Master's degree with 3+ years. The overall years minimum is set to 3 (the lower bound across both paths).
Primary location is Austin, TX; additional locations include Santa Clara, CA and Hillsboro, OR. The posted salary range ($141,910–$200,340/year) covers all US locations.
The role is hybrid (on-site + off-site split), not fully remote.
SOC classification is Medium confidence: this is a hardware/SoC verification role (RTL, presilicon, UVM testbenches) that sits at the intersection of hardware design verification and software QA/test engineering. 15-1253 (Software QA Analysts and Testers) is the closest available code; 15-1252 (Software Developers) is a plausible runner-up given the testbench development and infrastructure work.
AMBA protocol experience (CHI, AXI, AHB, APB) and industry-standard VIP usage are explicitly called out as required experience within the minimum qualifications block.
Emulation models and system simulation tools appear only under Preferred Qualifications, as does postsilicon validation experience.
Read the full posting
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