Broomfield, CO

Salary
$140,000–$240,000from the description
Posted
Jul 15, 2026
Location
Broomfield, CO
Last confirmed open
Jul 21, 2026

What this job asks for AI summary

A management role overseeing a global team of engineers who design flip-chip BGA packages for advanced ASICs used in AI, networking, high-performance computing, and 5G applications. The position combines hands-on technical leadership — covering high-speed SerDes, HBM, DDR5, and power delivery — with program management across 20+ concurrent package designs. Suited to a seasoned IC packaging engineer with at least a decade of flip-chip BGA experience and several years managing engineering teams.

Senior level · 12+ years · Denver-Aurora-Lakewood, CO · Bachelor's required · Full-time

Must have (4)
SerDessignal integrity (SI)power integrity (PI)PCB layout
Nice to have (5)
HBMDDR5SI/PI simulationDFxautomation scripting

Posted 3 times — it's one opening, so apply once.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

Why we read it this way (7)

This role is primarily a people-management position (leading a worldwide R&D team, 3+ years management required, hiring/mentoring/retention responsibilities), mapped to 11-3021. However, the role also demands deep hands-on IC package design expertise, making 15-1299 (Computer Occupations, All Other) a plausible runner-up — IC package design engineering does not map cleanly to any standard BLS computer/software SOC.

The job title says 'Manager' but the posting is placed through Actalent (a staffing/consulting firm) on behalf of what appears to be Broadcom. The primary work location is stated as Broomfield, CO, with Fort Collins and San Jose mentioned as secondary onsite preferences; the CBSA reflects Broomfield (Denver-Aurora-Lakewood metro).

The 12+ years experience requirement is specifically tied to flip-chip BGA package design, not general engineering; it is captured as the years demanded on that skill and also as the overall years minimum since it is the stated overall role-level gate.

Management experience (3+ years) is a hard gate per the Essential Skills section but names no specific technology, so it is reflected in the overall years minimum context and the seniority assessment rather than as a named skill.

HBM, DDR5, SI/PI simulation, DFx, mechanical/thermal modeling, and automation scripting appear under 'Additional Skills & Qualifications,' which functions as a preferred/nice-to-have section.

SerDes, SI, PI, ASIC co-design, PCB layout, and project management are all listed under 'Essential Skills' and are treated as hard gates.

Ignored 4 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): flip-chip BGA package design, ASIC package co-design, project management, mechanical/thermal modeling.

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