Silicon Design Verification Engineer, Devices and Services at Google
Mountain View, CA
$138,000–$198,000from the description
Jul 9, 2026
Mountain View, CA
Jul 21, 2026
What this job asks for AI summary
A mid-level hardware verification role focused on validating custom silicon for consumer devices. Day-to-day work involves building constrained-random verification environments in SystemVerilog and UVM, applying formal verification techniques, writing coverage measures, and collaborating with design engineers to debug and confirm correctness of complex digital blocks ahead of tape-out. Suits engineers with solid RTL-level verification experience across SoC components and interconnects.
Mid level · 4+ years · San Jose-Sunnyvale-Santa Clara, CA · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 160 people in the San Jose-Sunnyvale-Santa Clara, CA area plausibly meet what this posting asks for (software developers). range 65–240
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $217,796 (middle half $177,469–$231,052). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
The role is Silicon Design Verification — a hardware/EDA discipline that sits between software development (15-1252) and a more specialized hardware-verification occupation. 15-1252 is the closest available SOC code; 15-1299 (Computer Occupations, All Other) is a reasonable runner-up given the specialized nature of silicon DV work.
The posting explicitly labels this a 'Mid' experience level in its header framing ('Mid — Experience driving progress, solving problems, and mentoring more junior team members'), which aligns with the 4-year minimum requirement.
Degree requirement: the JD states 'Bachelor's degree … or equivalent practical experience.' Because equivalent experience is explicitly accepted, the degree requirement is set to None per schema rules — however, the JD does list a specific degree field (EE/CE/CS), so the gate is soft.
SystemVerilog and C/C++ are listed as alternatives in the minimum qualifications ('using SystemVerilog or C/C++'); UVM is required separately in the responsibilities section with firm language.
'Scripting languages' appears only under Preferred qualifications and names no specific tool, so it is marked preferred. It is retained because the JD explicitly calls it out as a preferred skill category.
Compensation is stated as $138,000–$198,000/year plus a 15% bonus target and equity; the bonus and equity are not captured in the comp fields but are noted here.
ARM and RISC-V are listed together as alternatives under Preferred qualifications ('ARM and RISC-V processor based DV').
Read the full posting
The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.