Design Infrastructure Engineer (Standard and Custom Cell Characterization)-HBM
Micron Technology · Richardson, TX
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Jun 28, 2026
Richardson, TX
Jul 21, 2026
What this job asks for AI summary
This role centers on building and maintaining characterization infrastructure for standard and custom cells across multiple process technologies, including Micron internal nodes and TSMC foundry nodes. The work spans Liberty model generation, multi-corner/multi-mode simulation flows, STA integration, and silicon correlation, all in support of High Bandwidth Memory product lines. It suits engineers with hands-on experience in cell characterization tools such as SiliconSmart or PrimeLib and a background in scripting-driven automation.
Mid level · National · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $116,580 (middle half $79,370–$157,500).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (8)
This role sits at the intersection of EDA infrastructure engineering, circuit characterization, and semiconductor design — it does not map cleanly to any standard SOC code. 15-1299 (Computer Occupations, All Other) is used as the best available fit; 15-1252 (Software Developers) is a plausible alternative given the emphasis on building scalable automation flows and infrastructure.
No work location is specified in the posting beyond Micron's general US presence. The job profile is listed as 'Systems Design Engineer 2', suggesting a mid-level role, though the scope of responsibilities (multi-process-node, multi-product-line ownership) could support a Senior classification. The posting was mapped to Mid given the 'Level 2' framing.
The degree requirement states 'Bachelors or Masters'; Bachelors is treated as the minimum hard gate.
SiliconSmart and PrimeLib are listed as interchangeable alternatives in the required qualifications ('Experience in SiliconSmart or PrimeLib is required'), so they are captured as a single skill with alternatives.
Python, Perl, and Tcl are listed as interchangeable scripting options in the required qualifications; Python is used as the primary with the others as alternatives.
CMOS circuit design is listed as a required fundamental ('strong fundamentals in CMOS digital and mixed-signal circuit design') — no specific named tool, but it is a concrete technical domain gate retained as a skill.
Agentic AI appears under Preferred Qualifications with 'willingness to learn' framing, making it a soft preferred signal rather than a genuine gate.
Ignored 4 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): Liberty modeling, CMOS circuit design, PHY design, TSV design.
Read the full posting
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