ASIC Design Engineer - New College Grad 2026
NVIDIA Corporation · Santa Clara, CA
$100,000–$189,750from the description
Jul 16, 2026
Santa Clara, CA
Jul 21, 2026
What this job asks for AI summary
A CPU logic design role focused on on-chip interconnect networks, cache coherency, and last-level caches. Day-to-day work involves micro-architectural definition, writing RTL, synthesis and timing closure, and collaborating with verification and implementation teams to meet power, area, and performance targets. Suited to early-career engineers with a strong grounding in computer architecture, ASIC design flow, and Verilog.
Junior level · National · Bachelor's required · Full-time
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
This is a hardware/RTL logic design role (CPU chip design), not a software development role in the traditional sense. SOC 15-1252 (Software Developers) is used as the closest available code; 15-1299 (Computer Occupations, All Other) is a reasonable alternative given the hardware-engineering nature of the work.
The posting covers two levels (Level 1 and Level 2) with overlapping salary bands: $100,000–$166,750 for Level 1 and $116,000–$189,750 for Level 2. The comp range reported spans both levels ($100,000–$189,750). The role targets recent graduates (BS or MS), placing it at the junior end of the career ladder.
Location is not specified in the posting; NVIDIA's primary US campus is Santa Clara, CA, but no city is stated, so the CBSA is left blank.
The requirements section lists 'computer architecture, cache coherency or high speed interconnects' as a strong background requirement using 'or' — cache coherency and high-speed interconnects are marked preferred as they are alternatives to the primary computer architecture requirement rather than independent hard gates.
Mentoring junior engineers is explicitly called 'a huge plus,' so it is not captured as a required skill.
'Equivalent experience' is accepted in lieu of a BS/MS degree per the posting; however, a BS is the baseline stated degree and is reported as the minimum formal degree requirement.
Ignored 5 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, timing analysis, ASIC design, floor-planning, computer architecture.
Read the full posting
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