Mixed Signal Verification Engineer
Retym, Inc · Austin, TX
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Jul 1, 2026
Austin, TX
Jul 20, 2026
What this job asks for AI summary
Mid level · 5+ years · National
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
UVM is listed under 'Preferred Qualifications' despite being central to the described testbench work; it is treated as preferred per section placement.
Synopsys and Cadence tool experience is explicitly called 'an advantage' under Preferred Qualifications.
The 'Additional Skills' section (verification methodologies, simulators, waveform viewers, coverage collection, scalable test cases) describes general competencies and soft skills rather than named tools, so no additional skill entries were emitted for those items.
SOC classification is a judgement call: the role is primarily verification/testing of mixed-signal hardware designs (closer to 15-1253), but the heavy SystemVerilog/UVM testbench coding component could also support 15-1252 Software Developers.
Seniority is assessed as Mid (5+ years stated, but the scope is a focused individual-contributor verification role without explicit ownership of a full component or cross-team technical leadership).
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): Behavioral Modeling.
Read the full posting
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