Senior FPGA Engineer
Inversion · Playa Vista, CA
$137,000–$193,000from the description
Jul 12, 2026
Playa Vista, CA
Jul 21, 2026
What this job asks for AI summary
A senior-level FPGA engineering role on an avionics team building digital systems for spacecraft that perform atmospheric reentry. Day-to-day work spans RTL design, simulation, timing closure, and hardware bring-up for RF, telemetry, and real-time signal processing applications across both flight and ground hardware. Suited to an experienced FPGA engineer comfortable owning the full development lifecycle and collaborating across DSP, RF, embedded, and electrical disciplines.
Senior level · 5+ years · Los Angeles-Long Beach-Anaheim, CA · Bachelor's required · Top Secret clearance · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $164,459 (middle half $130,334–$195,752). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (9)
The posting is simultaneously advertising a Senior FPGA Engineer role (base $137K–$193K) and a Staff FPGA Engineer level for exceptional candidates (base $161K–$221K, 8+ years required). The extracted fields reflect the Senior-level gate (5+ years); the Staff-level compensation range is noted here for reference.
FPGA engineering sits at the boundary of hardware design and embedded software; 15-1252 (Software Developers) is used because the role centers on RTL design, simulation, synthesis, and firmware-level implementation — active development work — rather than operating existing systems. 15-1299 (Computer Occupations, All Other) is a plausible alternative given the specialized hardware-design nature of the work.
The clearance requirement is stated as 'ability to obtain and maintain a U.S. security clearance up to Top Secret' — the candidate need not currently hold one, but must be eligible. This is treated as a hard gate.
VHDL, Verilog, and SystemVerilog are listed together with 'and/or' language in the requirements section; they are emitted as separate skills with each listed as an alternative to the others, since any one (or combination) satisfies the requirement.
MATLAB/Simulink, Python, C, and C++ are listed together as a group for algorithm handoff, modeling, and automation; they are emitted as separate skills with cross-alternatives, as the JD treats them interchangeably for this purpose.
The 'Desired Qualifications' section is clearly a secondary, optional block; all skills drawn from it are marked preferred.
The degree requirement is Bachelor's or Master's — Bachelor's is the minimum hard gate and is recorded accordingly.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): hardware-in-the-loop testing.
Requires a Top Secret clearance — the cleared population is a small fraction of this occupation, so the real candidate pool is materially smaller than the estimate below, which does not model clearance.
Read the full posting
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