Lead SoC Verification Engineer
Anodize · Los Altos, CA
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Jul 14, 2026
Los Altos, CA
Jul 21, 2026
What this job asks for AI summary
A lead-level role focused on establishing and executing verification methodology for a custom edge SoC at a stealth startup. Day-to-day work spans building scalable testbenches, developing block-level and full-chip verification plans, driving constrained-random and directed test development, and collaborating with design and software teams. Suits a seasoned ASIC verification engineer with a strong UVM background and experience seeing designs through to silicon.
Senior level · 10+ years · National
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $138,970 (middle half $107,524–$175,762).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
This role is SoC/ASIC design verification (DV) — a hardware engineering discipline. No standard SOC code cleanly covers it; 15-1252 (Software Developers) is used as the closest available code because the work involves writing testbenches, UVM libraries, and verification infrastructure in SystemVerilog/SystemC, but 15-1299 (Computer Occupations, All Other) is a plausible alternative. Confidence is Low due to this structural mismatch.
The title 'Lead' maps to advertised Senior; the 10+ years requirement and end-to-end SoC ownership scope also support Senior rather than Staff, as the role appears to be a senior IC contributor rather than a cross-team technical director.
Degree requirement: the JD states 'Bachelor's or Master's degree … or equivalent experience,' which means equivalent experience is accepted in lieu of a degree — treated as no hard degree gate.
AMBA CHI, AXI, AXI-S, and APB are listed together as a single interconnect-protocol requirement; they are emitted as separate skills because each is a distinct protocol standard.
SystemVerilog and SystemC are listed together ('System Verilog/System-C') as interchangeable fluency options — emitted as one skill with SystemC as the alternative.
The preferred qualifications (multi-media SoC, ARM cores, performance modeling, silicon bring-up) are explicitly under a 'Preferred Qualifications' heading and are marked accordingly.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): multi-media SoC verification, performance modeling.
Read the full posting
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