FPGA Developer
DRW · Chicago, IL
$225,000from the description
Jul 14, 2026
Chicago, IL
Jul 21, 2026
What this job asks for AI summary
An entry-level FPGA developer role at a proprietary trading firm, suited to candidates graduating between late 2026 and mid-2027. The work centers on building and optimizing ultra-low-latency trading systems in RTL (SystemVerilog, Verilog, or VHDL), including algorithmic strategies, exchange protocol adapters, and inter-application communication, with performance tuning and collaboration with experienced engineers.
Junior level · Chicago-Naperville-Elgin, IL-IN-WI · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 270 people in the Chicago-Naperville-Elgin, IL-IN-WI area plausibly meet what this posting asks for (software developers). range 100–350
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $137,335 (middle half $106,829–$171,337). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
This is an entry-level / new-grad role: the JD explicitly targets candidates graduating between December 2026 and June 2027 (Bachelor's, Master's, or PhD), so seniority is assessed as Junior despite the $225K base.
The title is 'FPGA Developer', which sits at the boundary between embedded/hardware-description-language work (15-1299) and software development (15-1252). The role ships proprietary trading software and low-latency systems in RTL/HDL alongside C/C++/Python, so 15-1252 is the primary classification with 15-1299 as the runner-up.
The compensation is listed as a single point ('$225,000') with no stated range; min and max are both set to 225,000.
The degree requirement is a hard gate (Bachelor's, Master's, or PhD in a named engineering/CS/math discipline), so Bachelor's is recorded as the minimum.
SystemVerilog, Verilog, and VHDL are presented as interchangeable alternatives ('modern System Verilog, Verilog or VHDL'); similarly C, C++, and Python are listed as alternatives for the language requirement.
FPGA is inferred as a hard requirement from the job title 'FPGA Developer' and the overall role context, even though the word 'FPGA' does not appear explicitly in the requirements bullet list.
Read the full posting
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