FPGA Design Engineer - Pittsburgh, PA at Quintech Electronics & Communications Inc
Pittsburgh, PA
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Jul 7, 2026
Pittsburgh, PA
Jul 21, 2026
What this job asks for AI summary
This role centers on designing and developing signal processing products using modern FPGA architectures, including high-bandwidth interfaces such as 100 Gigabit Ethernet and PCIe. The work involves collaborating with hardware and software teams across the full project lifecycle, with applications in wired and wireless communications. It suits engineers comfortable with HDL, networking protocols, timing analysis, and scripting in a US-citizen-only, security-clearance-eligible position.
Mid level · Pittsburgh, PA · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 30 people in the Pittsburgh, PA area plausibly meet what this posting asks for (software developers). range 6–45
Applicant volume Light — Few people clear these requirements, so an application that does clear them gets looked at. Worth applying to even if you miss a nice-to-have.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $127,238 (middle half $97,661–$159,195).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
The posting lists 'VDHL' which is clearly a typo for VHDL; extracted as VHDL.
The JD does not explicitly require a clearance — it states candidates must have the 'ability to meet eligibility requirements for security clearance,' which is a citizenship/eligibility gate, not a current clearance requirement. Clearance is therefore not marked as required.
A degree in 'Engineering or Science' is required; mapped to Bachelors as the minimum implied level (no specific degree level stated, but a professional engineering/science degree is the standard interpretation).
All skills appear in the 'Candidate Requirements' section and are treated as hard gates. JavaScript is an unusual requirement for an FPGA role and may reflect web-based tooling or internal dashboards; it is listed alongside the other required languages with no qualification.
No total years of experience are specified. The role's scope (contributing to product development, working as part of a team) suggests a Mid-level position despite no explicit seniority label.
SOC classification is Medium confidence: FPGA design engineering sits at the intersection of hardware and software; 15-1252 (Software Developers) is the closest fit given the primary focus on HDL/firmware development, with 15-1299 (Computer Occupations, All Other) as a reasonable alternative.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): Static Timing Analysis.
Read the full posting
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