Sr. Reliability/Verification Engineer at Ouster
San Francisco, CA
$140,000–$200,000from the description
Jul 29, 2026
San Francisco, CA
Sep 24, 2026
What this job asks for AI summary
A hardware reliability and verification engineering role on a small industrial autonomy team, responsible for designing test frameworks and validation strategies for compute, electromechanical, and safety-critical hardware platforms. Day-to-day work spans environmental stress testing (HALT, thermal cycling, vibration, EMI/EMC), electrical validation of vehicle wire harnesses and sensor interfaces, FMEA, and root cause analysis. Best suited for an experienced hardware reliability engineer with a background in rugged or industrial-grade systems.
Senior level · 8+ years · San Francisco-Oakland-Berkeley, CA · Full-time
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Why we read it this way (4)
This role is primarily hardware reliability and verification engineering — it centers on physical test execution (HALT, thermal cycling, EMI/EMC, vibration, ingress protection), FMEA, and RCA for electromechanical and compute hardware. 15-1253 (Software Quality Assurance Analysts and Testers) is the closest available SOC code given the verification/validation framing, but the work is overwhelmingly hardware-focused rather than software QA; 15-1252 is listed as an alternative since the role also involves hardware-software integration validation. Neither code is a perfect fit.
ISO 26262 (and functional safety standards generally) appear only under the 'Preferred experience' section, so they are marked as preferred rather than required.
The posting references San Francisco's Fair Chance Ordinance, strongly implying an SF Bay Area location, though no explicit city is stated.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): Root Cause Analysis.
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