Westminster

Salary
$160,000–$190,000
Posted
Jul 21, 2026
Location
Westminster
Last confirmed open
Jul 23, 2026

What this job asks for AI summary

A senior individual contributor role focused on building and leading FPGA and digital design verification infrastructure for aerospace communication hardware. Day-to-day work centers on developing UVMf-based testbenches, continuous integration and regression pipelines, and DPI-C interfaces connecting hardware models with existing MATLAB and Python tools. The role also carries a mentorship responsibility, guiding engineers across experience levels on modern verification methodologies.

Senior level · 9+ years · Austin-Round Rock-Georgetown, TX · Bachelor's required · Full-time

Pay in the description: $160,000–$190,000

Advertised as Principal, but the requirements read as Senior.

Must have (14)
FPGAVHDLVerilogSystemVerilogUVM or UvmfSystemCC++ or CDPI-CTLMQEMUVIPCILinuxXilinx
Nice to have (2)
MATLABPython

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

How this req sits in the market our data

Roughly 10 people in the Austin-Round Rock-Georgetown, TX area plausibly meet what this posting asks for (software developers). range 2–20

Applicant volume Light — Few people clear these requirements, so an application that does clear them gets looked at. Worth applying to even if you miss a nice-to-have.

What gives you an edge
UVM1%SystemVerilog2%VHDL3%Verilog3%

Rare in this occupation — lead with these, and say what you built with them.

What won't set you apart
Linux45%

Most people in this occupation already list these. Still required — just not what gets you shortlisted.

What the occupation pays Median $137,069 (middle half $106,287–$172,440). This posting is about at that midpoint.

Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.

Why we read it this way (5)

The title 'Principal Verification Engineer I' is unusual — 'Principal' suggests a top-of-ladder level, but the 'I' suffix implies an entry point within that band. The actual requirements (9+ years, expert-level FPGA verification, mentoring/leadership) support Senior rather than a true org-wide Principal scope; the role appears to be a senior individual contributor with a company-specific title convention.

The SOC classification is a close call: the role is primarily about building and leading verification/testbench infrastructure (closer to 15-1252 Software Developers) rather than executing QA test plans (15-1253). The alt code 15-1253 is noted given the heavy verification/testing focus.

MATLAB and Python are mentioned in the job duties as existing models the candidate will interface with via DPI-C, not as standalone required skills — they appear in narrative context rather than the requirements block, so they are marked preferred.

The posting does not explicitly state a work location city, but CesiumAstro is headquartered in Austin, TX; the CBSA is inferred from that.

The posting notes US person status requirements (ITAR compliance) but does not gate on a formal US government security clearance — clearance is set to None.

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