Senior Director, Physical Design & Backend Engineering (HPC)
Hop · Austin, TX
—
Jun 30, 2026
Austin, TX
Jul 21, 2026
What this job asks for AI summary
A senior leadership role overseeing the full RTL-to-GDS backend implementation cycle across HPC SoC and MCU programs, from physical design and timing closure through tape-out signoff. The position manages large, geographically distributed engineering teams across multiple concurrent programs, with direct accountability for hitting power, performance, and area targets. It suits a seasoned semiconductor physical design leader with 20+ years of experience and a track record of delivering complex SoC programs at advanced process nodes.
Principal level · 20+ years · National · Master's required
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (8)
No work location is specified in the posting; CBSA and state fields are left blank. The role leads globally distributed teams, so the primary base could be outside the US — the US-based flag defaults to true given the ambiguity.
SOC classification is a genuine judgment call: the role is explicitly a Senior Director with direct reports, budget ownership, and org-wide scope (11-3021), but the JD also demands deep hands-on technical expertise in physical design (RTL-to-GDSII, timing closure, etc.). 11-3021 was chosen as primary because people-management and organizational delivery are the stated primary accountabilities; 15-1299 is noted as the runner-up for the deep IC-level technical depth.
The title 'Senior Director' with org-wide scope across multiple programs and geographies maps to Principal on the seniority ladder — this is a top-of-org individual leadership role, not a single-team manager.
A Master's degree in Electrical Engineering, Computer Engineering, or a related field is explicitly required (not 'or equivalent experience'), so the degree requirement is set to Masters.
Skills such as 'advanced node implementation and signoff methodologies' and 'EDA vendors/tools' appear in the required technical expertise section; EDA tools is listed as preferred because the JD names no specific EDA product and the reference is to vendor partnership rather than hands-on tool use.
DFT appears only as a cross-functional partner team ('Partner with architecture, RTL, DFT…'), not as a required personal skill — listed as preferred accordingly.
Preferred qualifications (HPC/automotive domain experience, methodology/flow development, multi-geography experience) are captured where they map to named technical areas; purely domain or soft-skill preferences are omitted per schema rules.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): SoC design, MCU design, advanced node implementation.
Read the full posting
The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.