Junior FPGA Developer at Edgehog Trading
Chicago, IL
$100,000–$175,000from the description
Jun 30, 2026
Chicago, IL
Jul 21, 2026
What this job asks for AI summary
An FPGA engineering role at a proprietary options market-making firm, focused on designing and verifying RTL logic in Verilog or SystemVerilog for ultra-low-latency trading systems. Day-to-day work covers simulation testbenches, synthesis and timing closure, hardware bring-up, and debugging. The role suits early-career engineers with hands-on RTL experience who want to learn the high-frequency trading domain; no finance background is required.
Junior level · Chicago-Naperville-Elgin, IL-IN-WI · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 60 people in the Chicago-Naperville-Elgin, IL-IN-WI area plausibly meet what this posting asks for (software developers). range 35–110
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $137,335 (middle half $106,829–$171,337). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
This role is FPGA/RTL-focused hardware design — it sits at the boundary of hardware engineering and software development. SOC 15-1252 (Software Developers) is used as the closest match given the design-and-build nature of the work; 15-1299 (Computer Occupations, All Other) is a plausible alternative given the specialized hardware/RTL focus.
The posting explicitly accepts coursework, personal projects, or internship experience in lieu of professional experience, and no overall years of experience are stated — this is clearly an entry-level/junior role despite no explicit 'Junior' label in the title.
Degree requirement: the JD states 'BS or MS in Electrical Engineering, Computer Engineering, or a related field' as a qualification — treated as a hard Bachelors gate (the minimum of the two options).
Verilog and SystemVerilog are listed together as interchangeable RTL design languages ('Verilog or SystemVerilog') — emitted as a single requirement with each as an alternative for the other.
FPGA simulation tools (ModelSim, QuestaSim, Vivado, Quartus) are listed as 'e.g.' examples under the required qualifications section — treated as a hard gate on simulation tool familiarity, with all named tools captured as alternatives.
Python, C, and C++ are explicitly called out as 'a plus' in the qualifications section — marked as preferred.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): FPGA design.
Read the full posting
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