Front End Infrastructure Engineer
Saige Partners · Austin, TX
$145,600–$197,600
Jul 26, 2026
Austin, TX
Jul 28, 2026
What this job asks for AI summary
This role focuses on building and maintaining Front-End Design Verification (DV) flows and CAD infrastructure for large-scale semiconductor projects. Day-to-day work involves developing regression management tooling, debugging verification failures, supporting EDA tools (primarily Synopsys VCS), and managing version control workflows. It suits an experienced semiconductor/EDA infrastructure engineer comfortable working across verification, RTL, and CAD teams.
Senior level · 10+ years · Austin-Round Rock-Georgetown, TX · Bachelor's required · Contract
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (7)
This is explicitly a W2 contract position; C2C and W2 referral candidates are not eligible.
The experience requirement is tiered by degree: 10+ years with a Bachelor's, 8+ years with a Master's, or 6+ years with a PhD. The minimum (10 years with a Bachelor's) is used for total experience.
The SOC classification is Medium confidence — this role sits at the intersection of EDA tool support, CAD infrastructure, and verification flow development (software engineering for semiconductor tooling), which does not map cleanly to a single standard occupation. 15-1252 Software Developers was chosen because the primary work is building and maintaining software-based verification flows and tooling; 15-1299 is noted as a plausible alternative given the specialized EDA/CAD nature of the work.
xprop (X-propagation) is listed as a required configuration capability within VCS and IES environments, not a standalone tool — captured here as a named technical requirement per the posting.
'RTL architecture tools' is a generic phrase used in the posting; no specific product name is given.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): Front-End Design Verification (DV) flows, Regression management, ASIC/SoC development.
Posting is for a contract engagement — the market benchmarks below price full-time roles, so read the comp comparison with that in mind.
Read the full posting
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