Princeton, NJ

Salary
$150,000–$235,000from the description
Posted
Jul 19, 2026
Location
Princeton, NJ
Last confirmed open
Jul 21, 2026

What this job asks for AI summary

This role centers on designing and implementing low-latency FPGA-based control and signal processing for a neutral-atom quantum computer. Day-to-day work spans RTL design, PS firmware, and hardware-in-the-loop validation, with a focus on sub-nanosecond RF pulse synchronization and microsecond-timescale adaptive execution. It suits engineers with a background in digital logic design or verification for FPGAs or ASICs, particularly those familiar with high-throughput, multi-clock-domain designs.

Mid level · New York-Newark-Jersey City, NY-NJ-PA · Full-time

Must have (2)
FPGA or Asicdigital logic verification
Nice to have (2)
Xilinx RFSoCPS firmware

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

Why we read it this way (7)

The role is highly specialized in FPGA/RTL engineering for quantum computing control systems. 15-1252 (Software Developers) is the closest available code given the emphasis on designing, implementing, and verifying RTL and firmware; 15-1299 (Computer Occupations, All Other) is a reasonable runner-up given the hardware-adjacent nature of the work.

The posting is based in Princeton, NJ, which falls within the New York-Newark-Jersey City CBSA (35620); no remote option is mentioned.

Digital logic design or verification for FPGAs or ASICs is stated as 'essential' — treated as a hard gate. RTL design and hardware-in-the-loop validation are explicitly called out as core responsibilities within the same required framing.

High-throughput multi-clock domain design and Xilinx/AMD RFSoC familiarity are explicitly flagged as 'preferred' in the posting.

No minimum years of experience or degree requirement is stated. Seniority is assessed as Mid given the 'co-owner growing into full subsystem ownership' framing, which implies an earlier-career trajectory rather than an already-senior engineer.

No quantum physics knowledge is required per the posting.

Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, hardware-in-the-loop validation, multi-clock domain design.

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