Verification Engineer at Broadcom
Fort Collins, CO
$121,900–$195,000from the description
Jul 13, 2026
Fort Collins, CO
Jul 21, 2026
What this job asks for AI summary
A senior verification engineering role focused on ASIC IP blocks, covering both block-level and system-level work. Day-to-day responsibilities include building and maintaining SystemVerilog/UVM testbenches, writing Python behavioral models, debugging simulation failures, and maintaining regression frameworks. Suited to engineers with deep RTL verification experience who are comfortable working across design, architecture, and verification teams on complex semiconductor projects.
Senior level · 8+ years · National · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $106,594 (middle half $82,076–$136,109). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
No work location is specified in the posting beyond 'outside USA' boilerplate; CBSA and state are left blank. The compensation range (USD 121,900–195,000/year) suggests a US-based role.
SOC classification is a genuine judgment call: the role is squarely in hardware/ASIC design verification (testbench authoring, UVM environments, simulation debugging), which maps most naturally to 15-1253 (Software QA Analysts and Testers). However, the emphasis on building behavioral models in Python and maintaining regression frameworks also has a software-development flavor (15-1252). 15-1253 is chosen as primary because verification — not feature development — is the stated core mission.
OVM is listed as an alternative to UVM since the JD explicitly pairs them ('UVM/OVM') as interchangeable options.
Firmware development, formal verification, and AI-assisted development tools all appear under the 'Preferred Qualifications' section and are marked accordingly.
The job title is not stated in the posting; advertised seniority is therefore Unspecified. The 8+ years requirement and scope (block- and system-level verification ownership) support a Senior classification.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): firmware development, AI-assisted development tools.
Read the full posting
The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.