Design Verification Engineer at Broadcom
Broomfield, CO
$143,800–$230,000from the description
Aug 4, 2026
Broomfield, CO
Nov 9, 2026
What this job asks for AI summary
A design verification engineer role at Broadcom's ASIC Products Division, focused on modeling and verifying complex digital and mixed-signal IP blocks used in custom ASIC development. The role involves defining verification plans, building UVM-based testbench environments, developing test cases, achieving coverage closure, and debugging RTL and gate-level simulations. Candidates with 12+ years of verification experience and deep SystemVerilog/UVM expertise are the target profile.
Senior level · 12+ years · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 5, 2026. It is a model, not a headcount.
Why we read it this way (6)
No specific work location or CBSA is stated in the posting; the role appears to be US-based (legal authorization to work in the US is required) but no city or region is given.
The degree requirement is a BS in EE/CE with 12+ years, or an MS in EE/CE with 10+ years. Since a bachelor's degree is the minimum path, the degree requirement is set to Bachelors. The MS path reduces the experience floor to 10 years; 12 is used as the overall years minimum reflecting the BS path.
Perl and Python are listed together as a single requirement ('Perl/Python'); they are treated as interchangeable alternatives for that requirement. Tcl is listed separately in the same requirement clause.
DesignSync and git are listed together as version control options; both are captured, with git also listed as an alternative to DesignSync.
Emulation platforms (Palladium, Veloce, Zebu) and FPGA (Xilinx) are explicitly listed under the 'plus' section, as are formal verification, Tessent/iJTAG, and co-simulation experience.
SOC classification as 15-1252 (Software Developers) reflects that the primary work is writing and building verification environments, testbenches, and behavioral models — code-centric engineering work. 15-1299 is noted as a runner-up given the specialized EDA/ASIC verification domain.
Read the full posting
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