Senior FPGA Engineer at Ralliant
Beaverton, OR
$103,500–$191,900from the description
Jul 20, 2026
Beaverton, OR
Jul 23, 2026
What this job asks for AI summary
A senior-level FPGA engineering role focused on designing measurement systems and subsystems for high-speed signal and electronic test applications. Day-to-day work involves implementing FPGA logic in Verilog/SystemVerilog, managing project schedules and risks within an Agile framework, and conducting peer reviews. The role suits an experienced hardware engineer with a background in digital design, ideally with familiarity in DSP concepts, serial data protocols, and FPGA verification methods.
Senior level · 5+ years · Portland-Vancouver-Hillsboro, OR-WA · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 75 people in the Portland-Vancouver-Hillsboro, OR-WA area plausibly meet what this posting asks for (software developers). range 45–110
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $159,430 (middle half $128,996–$177,877). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (9)
FPGA engineering sits at the boundary of hardware design and software development; 15-1252 (Software Developers) is the closest SOC match for RTL/HDL design work, but 15-1299 (Computer Occupations, All Other) is a reasonable alternative given the hardware-centric nature of the role.
The minimum experience requirement is 5+ years; 10+ years is listed only under Preferred Qualifications.
A Bachelor's degree in Electrical Engineering or Computer Engineering is a hard gate; a Master's or PhD is listed as preferred.
The posting references ITAR compliance — candidates must be US Persons or obtain export authorization. This is not a formal security clearance requirement but does restrict the eligible candidate pool.
Verilog and SystemVerilog are listed together with 'and/or', so SystemVerilog is captured as an alternative to Verilog rather than a separate skill.
Intel FPGA and Xilinx FPGA tools are listed together under Preferred Qualifications and are treated as interchangeable alternatives for that preferred requirement.
TCL and Python are listed as scripting language examples under Preferred Qualifications; Python is captured as an alternative to TCL since both satisfy the same scripting requirement.
The role is hybrid (Beaverton, OR), not fully remote.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): FPGA design, serial data link protocols.
Read the full posting
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