Senior ASIC Design Engineer at HP
Vancouver, WA
$116,150–$182,400from the description
Jul 28, 2026
Vancouver, WA
Jul 29, 2026
What this job asks for AI summary
This role is on HP's R&D digital ASIC design team in Vancouver, Washington, responsible for developing the main controller silicon for HP printers. The engineer will own functional blocks and subsystems through the full design cycle — RTL coding, verification, silicon validation, and FPGA prototyping — while collaborating with internal and external partners on specifications, roadmaps, and firmware integration. It suits an experienced hardware engineer with deep ASIC/SOC design flow expertise.
Senior level · 8+ years · Portland-Vancouver-Hillsboro, OR-WA · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 15 people in the Portland-Vancouver-Hillsboro, OR-WA area plausibly meet what this posting asks for (software developers). range 3–25
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $159,430 (middle half $128,996–$177,877). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 29, 2026. It is a model, not a headcount.
Why we read it this way (6)
The SOC code is a judgment call: ASIC/SOC hardware design sits at the boundary of electrical engineering and software development. 15-1252 (Software Developers) is the closest available code given the RTL/HDL coding and verification work; 15-1299 (Computer Occupations, All Other) is a reasonable alternative for hardware-focused digital design roles not well captured by standard software codes.
Synopsys and Cadence EDA tools are listed together as a paired requirement covering simulation, synthesis, STA, and formal/assertion-based verification; both are marked required as the posting treats them as a combined toolchain.
Git, Subversion, and GitHub are listed together as code base management options; Git is the primary name with the others as alternatives.
The 'big plus' domain areas — Laserjet printing technology, ARM microprocessor subsystem, DDR/Flash/eMMC memory subsystems, design flow automation scripting, and AI Copilot/LLM tools — are explicitly framed as preferred extras, not gates.
The degree requirement states 'BS or MS … or equivalent'; because equivalent experience is accepted, the degree requirement is set to Bachelors (the minimum named degree) rather than None, but candidates with equivalent VLSI experience are also considered per the posting.
The compensation range ($116,150–$182,400/year) is stated as applicable to US candidates only and may vary by location.
Read the full posting
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