FPGA Design Engineer
Actalent · Melbourne, FL
$75–$90/hrfrom the description
Jul 28, 2026
Melbourne, FL
Jul 29, 2026
What this job asks for AI summary
This fully onsite role in Melbourne, FL involves leading full-lifecycle FPGA development for a cryptography platform, covering architecture definition, RTL implementation, verification, and system integration. The ideal candidate brings deep expertise in high-speed interfaces (PCIe, 100G+ Ethernet, DDR4/5), RTL design in Verilog/VHDL, and FPGA toolchains from Xilinx and Intel. The position also includes mentoring junior engineers and collaborating across hardware and software teams.
Senior level · 8+ years · Palm Bay-Melbourne-Titusville, FL · Secret clearance · Contract
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $134,657 (middle half $104,151–$166,625). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 29, 2026. It is a model, not a headcount.
Why we read it this way (10)
SOC classification is a judgement call: FPGA design sits between hardware engineering and software development. 15-1252 (Software Developers) is used because the primary day-to-day work is writing and verifying RTL code (Verilog/VHDL/SystemVerilog) and building testbenches — activities BLS maps to software development. 15-1299 (Computer Occupations, All Other) is the runner-up for roles that don't fit neatly into standard software developer categories.
The posting lists 'Verilog/VHDL' as a single combined requirement; both are captured as separate skills since they are distinct languages that are both used in FPGA design, not interchangeable substitutes.
RTL design is listed as a required skill but is a methodology rather than a named tool; it is included here because it is the core technical discipline explicitly gated in the Essential Skills section.
The posting states the position can be 'Contract-to-Hire or just long term Contract (w2)' — classified as Contract accordingly.
An active DoD Secret clearance is explicitly required ('Must have an Active DoD Secret Clearance').
FPGA timing closure and FPGA power estimation are included as required skills because they are explicitly called out as proficiency requirements in the Essential Skills section, even though they describe capabilities rather than named tools.
'Lattus Diamond' in the posting appears to be a typo for 'Lattice Diamond'; captured under the canonical name.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design.
Requires a Secret clearance — the cleared population is a small fraction of this occupation, so the real candidate pool is materially smaller than the estimate below, which does not model clearance.
Posting is for a contract engagement — the market benchmarks below price full-time roles, so read the comp comparison with that in mind.
Read the full posting
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