ASIC Verification Engineer at Ericsson
Austin, TX
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Jul 26, 2026
Austin, TX
Jul 29, 2026
What this job asks for AI summary
This is a senior-level ASIC/IP design verification engineering role at Ericsson's Austin semiconductor center, focused on 5G network chip development. The engineer will lead block- and top-level RTL verification efforts, architect UVM/SystemVerilog testbenches from scratch, and contribute to hardware emulation and software-driven verification. The role suits an experienced verification professional with deep RTL debugging skills and familiarity with at least one domain such as SerDes, PCIe, or Ethernet.
Senior level · 10+ years · Austin-Round Rock-Georgetown, TX · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 10 people in the Austin-Round Rock-Georgetown, TX area plausibly meet what this posting asks for (software developers). range 4–20
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $137,069 (middle half $106,287–$172,440).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 29, 2026. It is a model, not a headcount.
Why we read it this way (6)
The posting requires knowledge of 'at least one' technology domain (SerDes, PCIe, ARM subsystems, DSPs/accelerators, or Ethernet) — this is a hard gate on domain familiarity, but any single domain satisfies it; the specific technologies are listed as preferred when a candidate has experience across multiple domains.
Scripting language proficiency (TCL, Python, Perl, or similar) is listed under Required Qualifications; TCL is used as the primary skill name with Python and Perl as named alternatives since the posting treats them as interchangeable.
RTL verification is listed as a required skill but is a broad capability rather than a named tool; it is included because the posting explicitly gates on 'IP, ASIC, SoC, or FPGA RTL verification' experience.
No compensation figures are stated — the posting notes salary depends on location and candidate factors without providing a range.
The degree requirement is BS or MS in EE, CS, or related field; BS is the minimum stated, so Bachelors is used.
SOC classification is Medium confidence: ASIC design verification is closest to Software Developers (15-1252) given the heavy testbench coding and RTL modeling work, but 15-1299 (Computer Occupations, All Other) is a reasonable alternative given the specialized hardware verification nature of the role.
Read the full posting
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