ASIC SoC Verification Engineer at Ericsson
Austin, TX
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Jul 26, 2026
Austin, TX
Jul 29, 2026
What this job asks for AI summary
This role focuses on top-level verification of complex ASICs and SoCs at Ericsson's Austin site, covering designs that include hundreds of processor cores, DSPs, ARM cores, and high-speed interfaces. The engineer will develop and execute test cases across SystemC/TLM simulation, RTL, and hardware emulation environments, define verification strategies, and collaborate with cross-functional teams to ensure comprehensive coverage. It suits an experienced hardware verification engineer with a strong SoC-level background.
Senior level · Austin-Round Rock-Georgetown, TX · Bachelor's required · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (5)
ASIC/SoC top-level verification is a specialized hardware discipline that sits between software QA (15-1253) and general computer occupations (15-1299); 15-1299 was chosen as the primary code because the work is hardware-centric RTL/emulation verification rather than software testing, but 15-1253 is a reasonable runner-up given the test-development and coverage focus.
No explicit total years of experience are stated in the posting; seniority is inferred as Senior from the scope ('top-level' SoC verification, cross-functional collaboration, defining verification strategies) and the expectation of a 'proven background'.
Hardware emulation appears in both the required section ('Familiarity with hardware emulation platforms') and the preferred section ('Hardware emulation or silicon-level verification experience'); it is captured once as required based on its placement in the required block.
Salary range is described as location- and candidate-dependent but no figures are provided.
The posting states 'BS degree in a related discipline required, MS preferred'; a Bachelor's is the hard minimum.
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