SoC Performance Verification Engineer - Senior at Microsoft
Raleigh, NC
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Aug 5, 2026
Raleigh, NC
Sep 24, 2026
What this job asks for AI summary
This hardware verification engineering role focuses on building and owning performance verification methodology for a SoC program (Cobalt). The engineer will develop test plans, verification environments, and tooling; author and debug performance tests on emulation platforms; and collaborate with architecture and IP teams to correlate performance indicators and drive design quality. The role suits someone with deep SoC/computer-architecture verification experience through at least one full tapeout cycle.
Senior level · 5+ years · Full-time
“or” means any one of them counts — you don't need all of them.
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How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $106,594 (middle half $82,076–$136,109).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 7, 2026. It is a model, not a headcount.
Why we read it this way (6)
The role is hardware/SoC performance verification (RTL/emulation), which sits closer to hardware design verification than traditional software QA; 15-1253 is the best available fit, with 15-1252 as a reasonable alternative given the significant test-development and tooling work.
Degree requirement: the JD lists a tiered education+experience ladder (Doctorate+1yr / Master's+4yr / Bachelor's+5yr / equivalent experience). Because equivalent experience is explicitly accepted in lieu of any degree, the degree requirement is set to None.
The overall years minimum is set to 5, reflecting the minimum years required under the Bachelor's path (the lowest-degree tier). The JD also separately states '6+ years of experience working on Computer Architecture and SoC design and verification' — this is a per-domain requirement rather than a clean role-level gate, but hiring managers should note it as a practical floor.
Export-control note: the posting requires proof of citizenship, US residency, or protected status (e.g., lawful permanent resident) as a condition of employment due to access to export-controlled information (ITAR/EAR). This is not a security clearance but is a meaningful eligibility gate.
ARM architectures and protocols, CPU architecture/firmware, and coherent/non-coherent fabric IPs appear in a list at the end of the posting without a clear 'Required' or 'Preferred' heading; they are treated as preferred/nice-to-have context rather than hard gates.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): CPU architecture.
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