Senior Memory Controller Verification Engineer
NVIDIA Corporation · Santa Clara, CA
$168,000–$310,500from the description
Jul 9, 2026
Santa Clara, CA
Jul 20, 2026
What this job asks for AI summary
A senior role focused on verifying GPU memory subsystem IP, working alongside design and architecture teams. Day-to-day work involves building testbenches and verification infrastructure, developing and executing functional and performance test plans, closing code and functional coverage, and supporting post-silicon debug. Suits experienced ASIC verification engineers with a SystemVerilog/UVM background, ideally with exposure to memory controller designs.
Senior level · 6+ years · Santa Clara, CA · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 50 people in the Santa Clara, CA area plausibly meet what this posting asks for (software developers). range 15–80
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $217,796 (middle half $177,469–$231,052). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
The role is ASIC/hardware verification engineering — primarily building testbenches, BFMs, checkers, and driving test plans for RTL/GPU IP. It sits between 15-1252 (Software Developers, for the infrastructure/automation code written) and 15-1253 (QA Analysts and Testers, for the verification/coverage closure work); 15-1252 was chosen as primary because the JD emphasizes developing verification infrastructure and code.
The posting covers two internal levels (Level 4 and Level 5) with distinct salary bands: $168,000–$264,500 (L4) and $196,000–$310,500 (L5). The pay band figures reflect the full combined range across both levels.
Location is listed as #LI-Hybrid with no explicit city; Santa Clara, CA (NVIDIA HQ) is inferred as the primary work location.
Degree requirement is None — the JD states 'BS / MS or equivalent experience', explicitly accepting equivalent experience in lieu of a formal degree.
Debug tools (Debussy/GDB) are listed together in the required section as examples; Debussy is captured as the primary skill with GDB noted as an alternative context tool. Verdi (the modern successor to Debussy) is a natural alternative.
C/C++ and scripting (Python/Perl/Shell) appear under 'Ways to stand out from the crowd' (the preferred/nice-to-have section), as does prior dynamic memory controller experience — all marked preferred accordingly.
Read the full posting
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