Senior ASIC Design Engineer - DFX
NVIDIA Corporation · Santa Clara, CA
$168,000–$310,500from the description
Jul 9, 2026
Santa Clara, CA
Jul 20, 2026
What this job asks for AI summary
This role sits within a DFT methodology team focused on the architecture, design, and verification of DFT intellectual property — including fuse controllers — for complex next-generation SoC chips. The work spans the full silicon lifecycle, from RTL development and full-chip verification through post-silicon bring-up and debug on ATE. It suits an experienced engineer with deep SoC and DFT expertise who is also comfortable mentoring others.
Senior level · 6+ years · Santa Clara, CA · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 370 people in the Santa Clara, CA area plausibly meet what this posting asks for (software developers). range 140–580
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $217,796 (middle half $177,469–$231,052). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
This is an ASIC/hardware design role (DFT — Design for Test / Design for X), which sits outside the standard software-developer SOC taxonomy. 15-1252 (Software Developers) is used as the closest available code because the role involves RTL design, verification, and scripting; 15-1299 (Computer Occupations, All Other) is the runner-up. Neither code is a precise fit for semiconductor/ASIC engineering.
The JD accepts a Bachelor's + 8 years OR a Master's + 6 years; because equivalent experience is accepted in lieu of a degree, the degree requirement is set to None. The overall years minimum reflects the lower bound (6 years with a Master's).
Compensation is quoted across two internal levels (L4: $168,000–$264,500; L5: $196,000–$310,500). The min and max reported here span the full range across both levels.
UVM is explicitly called out as 'a plus' in the requirements section, so it is flagged as preferred.
Location is not explicitly stated in the posting; Santa Clara, CA (NVIDIA HQ) is inferred as the most likely work location.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, SoC architecture.
Read the full posting
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