Senior ASIC Design Engineer
NVIDIA Corporation · Santa Clara, CA
$136,000–$264,500from the description
Jul 13, 2026
Santa Clara, CA
Jul 20, 2026
What this job asks for AI summary
This role sits within a System ASIC team responsible for designing and integrating system-level hardware modules — including reset and boot controllers, floorsweep logic, and in-silicon measurement blocks — into complex GPU and SoC chips. Day-to-day work spans RTL design, logic synthesis, timing analysis, and SOC-level integration, with involvement in silicon bring-up. It suits engineers with solid ASIC or SOC integration experience and scripting proficiency.
Senior level · 5+ years · Remote · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 155,000 people nationally plausibly meet what this posting asks for (software developers). range 65,000–232,500
Applicant volume Heavy — This req sits in a large pool with little in its requirements to thin it, and auto-apply tools fire at everything in the occupation. Applying early and leading with the rare skills below is what gets read.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (8)
The posting is for an ASIC/hardware design role (RTL, synthesis, SoC integration), which sits at the boundary of hardware engineering and software development. SOC 15-1252 (Software Developers) is used as the closest available code; 15-1299 (Computer Occupations, All Other) is a reasonable alternative given the hardware-design focus.
The job title is '#LI-Hybrid', indicating a hybrid work arrangement per the posting itself. The caller has overridden this to remote=true, so no metro has been inferred.
Two salary bands are given: $136,000–$218,500 (Level 3) and $168,000–$264,500 (Level 4). The min and max across both bands are reported ($136,000 and $264,500); the overlap range ($168,000–$218,500) applies to candidates who qualify for either level.
Perl, Python, and C++ are listed together under the required scripting/coding requirement ('Strong coding skills in Perl, Python, C++, or other industry-standard scripting languages'). Perl is emitted as the primary with Python and C++ as alternatives for that single requirement; Python and C++ are also separately listed under the preferred 'Ways to stand out' section for hands-on programming experience.
Degree requirement is set to None because the JD explicitly accepts 'equivalent experience' in lieu of a BS/MS.
The 5+ years figure covers ASIC design or SoC integration experience broadly, not a specific named technology, so it is captured as the role-level minimum experience.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, timing analysis, ARM CPU/SoC architecture.
Caller marked this a fully-remote role — scored against the national candidate pool.
Read the full posting
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