SOC Design Verification Engineer – Data Center Solutions at Qualcomm
San Diego, CA
$115,600–$173,400from the description
Jun 30, 2026
San Diego, CA
Jul 21, 2026
What this job asks for AI summary
A design verification role focused on next-generation Data Center SoCs, covering areas such as multi-core CPU systems, cache coherency, DDR/HBM memory, high-speed interfaces, and AI/ML accelerators. Day-to-day work involves building SystemVerilog/UVM testbenches, writing assertions and coverage models, debugging RTL and integration issues, and driving coverage closure. Suited to engineers with at least two years of SoC or IP-level verification experience.
Mid level · 2+ years · National · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $106,594 (middle half $82,076–$136,109). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
The posting covers a range of seniority levels — it explicitly states 'Senior positions to be offered to candidates with proven expertise' and the minimum gate is 2+ years (or 1+ year with a Master's, or a PhD). The seniority is assessed at the minimum/entry point of the range (Mid), but hiring managers should note this requisition may fill both mid-level and senior-level roles.
No specific work location or CBSA is stated in the posting; Qualcomm's Data Center SoC teams are primarily based in San Diego, CA, but this cannot be confirmed from the text alone.
The degree requirement is a Bachelor's as the minimum hard gate; a Master's or PhD reduces the experience requirement but is not itself required.
Coverage-Driven Verification and SVA (Assertion-Based Verification) are listed explicitly in the required 'Strong knowledge of' section and are treated as hard gates, even though they are methodologies rather than discrete tools.
All preferred qualifications (CPU verification, cache coherency protocols, DDR/HBM, PCIe/Ethernet/CXL, AI/ML accelerator verification, PSS, Formal Verification, emulation platforms, Python) appear under an explicit 'Preferred Qualifications' heading.
The alt SOC (15-1252 Software Developers) is noted because hardware design verification at this level involves substantial environment and testbench development in SystemVerilog/UVM and C, which overlaps with software development work; however, the primary function is verification/testing of silicon.
Read the full posting
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