FPGA Firmware Engineer / FPGA Design Engineer at Qualcomm
San Diego, CA
$115,600–$173,400from the description
Jul 15, 2026
San Diego, CA
Jul 21, 2026
What this job asks for AI summary
An ASIC engineering role focused on the design, modeling, verification, and documentation of IP blocks and SoCs for high-performance, low-power semiconductor products. Day-to-day work spans creating circuit specifications and logic designs, running flows from RTL through synthesis, place and route, and timing/power analysis, and writing technical documentation. Suited to engineers with a background in ASIC design or verification who are comfortable working across hardware and software teams.
Mid level · 2+ years · San Diego, CA · Bachelor's required · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (7)
The role is ASIC/hardware engineering — chip design, verification, and implementation — which does not map cleanly to any standard software or IT SOC code. 15-1299 (Computer Occupations, All Other) is the closest available fit; 15-1252 (Software Developers) is noted as a runner-up because RTL/HDL design shares some software-development characteristics.
The minimum qualification accepts a Bachelor's + 2 years OR a Master's + 1 year OR a PhD with no experience. Bachelor's is treated as the minimum hard-required degree since it is the lowest-bar path.
The job posting does not specify a city; Qualcomm's primary engineering campus is in San Diego, CA, which is used as the default location.
Most skills (RTL to GDS flow, Virtuoso, scripting, design verification, synthesis, place and route) appear only in the Preferred Qualifications or Principal Duties sections, not in the Minimum Qualifications block, so they are marked preferred. Only ASIC design experience itself is a hard gate per the Minimum Qualifications.
The 'scripting tools and programming languages' preferred requirement names no specific language or tool, so it is captured generically as 'scripting languages'; no specific tool could be extracted.
Compensation is stated as an annual pay range of $115,600–$173,400, plus discretionary bonus and RSU grants.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): ASIC design, RTL design, RTL to GDS flow.
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