Sr. / Staff ASIC Digital Design Engineer at SK hynix memory solutions America Inc.
San Jose, CA
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Jul 15, 2026
San Jose, CA
Jul 21, 2026
What this job asks for AI summary
This role sits within an ASIC implementation team, focused on DFT planning and integration, logic synthesis, static timing analysis, and power/IR analysis across full-chip and block-level designs. The work involves building and maintaining automated sign-off flows, managing ATPG and ATE interfaces, and collaborating with RTL and physical design teams to hit tapeout milestones. It suits an experienced digital design engineer with a strong background in front-end EDA tooling and low-power design methodologies.
Senior level · 6+ years · San Jose-Sunnyvale-Santa Clara, CA · Bachelor's required · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 1,150 people in the San Jose-Sunnyvale-Santa Clara, CA area plausibly meet what this posting asks for (software developers). range 230–1,700
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $217,796 (middle half $177,469–$231,052).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
This is an ASIC Digital Design / DFT role — it sits at the boundary of hardware engineering and EDA tool flows rather than traditional software development. 15-1252 (Software Developers) is used as the closest available code given the heavy scripting, flow automation, and tool-driven engineering work; 15-1299 (Computer Occupations, All Other) is a reasonable runner-up given the specialized semiconductor EDA nature of the work.
The experience requirement has two paths: Bachelor's + 8 years OR Master's + 6 years. The minimum across both paths is 6 years (Master's route), so the overall years minimum is set to 6. The degree requirement is set to Bachelor's as the minimum formal degree stated.
Scripting languages (Tcl, Perl, Python, Shell) are listed under Required Qualifications with the qualifier 'familiarity with' — however, they appear in the required section alongside firm requirements, so they are treated as hard gates. 'AI-assisted flow experience is a plus' is explicitly called optional and is omitted as it names no specific tool.
No compensation figures are provided — the posting describes a qualitative, location/grade-adjusted salary policy only.
Location is inferred as San Jose/Silicon Valley area based on SK Hynix Memory Solutions America's known headquarters in San Jose, CA; the posting does not explicitly state a city.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): Voltage drop analysis, CDC/RDC/Lint checks, Crosstalk analysis.
Read the full posting
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