Sr. Staff / Principal Firmware Engineer - Flash Interface Layer (FIL) at SK hynix memory solutions America Inc.
San Jose, CA
$165,000–$220,000from the description
Jul 26, 2026
San Jose, CA
Jul 28, 2026
What this job asks for AI summary
A firmware engineering role focused on designing and implementing code for the Flash Interface Layer of SSDs, including NAND management algorithms and error control coding. The work involves integrating firmware modules, debugging on FPGA/ASIC environments using tools like JTAG, and writing device drivers in embedded controller environments. Suited to engineers with deep embedded C/C++ and NAND flash experience.
Senior level · 5+ years · San Jose-Sunnyvale-Santa Clara, CA · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 120 people in the San Jose-Sunnyvale-Santa Clara, CA area plausibly meet what this posting asks for (software developers). range 30–180
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $217,796 (middle half $177,469–$231,052). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
The posting does not name a specific city; SK Hynix Memory Solutions America is headquartered in San Jose, CA, so the CBSA is inferred from that. If the role is at a different site, the metro may differ.
C and C++ are listed together as alternatives ('C or C++') — both are emitted as a single requirement with the other as an alternative.
FPGA and ASIC appear together as the debugging environment; emitted as one skill with ASIC as an alternative.
JTAG and In-Circuit Emulator are listed as examples of debugging tools; emitted as one skill with ICE as an alternative.
ARM architecture understanding and Linux kernel experience appear under 'Preferred Qualifications' and are marked accordingly.
The degree requirement is a BS in CS or EE; an MS is stated as preferred, so the minimum hard requirement is a Bachelor's degree.
Read the full posting
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