Design Verification Engineer at MatX
Mountain View, CA
$120,000–$475,000from the description
Jul 14, 2026
Mountain View, CA
Jul 21, 2026
What this job asks for AI summary
A silicon verification engineering role focused on AI accelerator chips, covering compute, memory management, and high-speed connectivity. The work involves building testbenches, developing verification methodology, and driving coverage closure from block level through full-chip and system validation to tapeout. Suited to engineers with hands-on UVM and SystemVerilog experience who have taken designs from specification to production silicon.
Senior level · San Jose-Sunnyvale-Santa Clara, CA · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 20 people in the San Jose-Sunnyvale-Santa Clara, CA area plausibly meet what this posting asks for (computer occupations, all other). range 4–25
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $188,486 (middle half $139,113–$224,920). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (5)
This is a silicon/hardware verification engineering role — not a software development role in the traditional sense. SOC 15-1299 (Computer Occupations, All Other) is the best available fit for RTL/silicon verification engineers; 15-1252 (Software Developers) is the runner-up given the heavy use of SystemVerilog, Python, and C/C++ for testbench and verification IP development.
The posting advertises three compensation tiers (Early Career $120K–$250K, Mid Career $175K–$362.5K, Senior Career $250K–$475K). The bottom of the pay band/max reflect the full range across all tiers; the role is being filled at multiple levels simultaneously.
Emulation/prototyping platform experience and silicon debug/bring-up experience are explicitly called out as 'a plus' — listed as preferred.
The role is hybrid (Mountain View office Tues–Thurs, remote Mon & Fri); it is not fully remote.
No minimum total years of experience is stated; seniority is assessed as Senior based on the scope of responsibilities (concept-to-silicon ownership, sign-off reviews, tapeout milestones) and the production-level experience required across multiple advanced verification methodologies.
Read the full posting
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