Santa Clara, CA

Salary
$200,000–$500,000
Posted
Jul 26, 2026
Location
Santa Clara, CA
Last confirmed open
Jul 28, 2026

What this job asks for AI summary

This role owns the functional safety architecture for a Physical AI System-on-Chip (SoC) at an early-stage semiconductor company. The architect defines safety goals, leads hazard and fault analyses, specifies hardware safety mechanisms, and builds the safety case across the full silicon lifecycle from architecture through tape-out and production. It suits a seasoned safety engineer with deep ISO 26262 and IEC 61508 expertise who can drive cross-disciplinary requirements across silicon, firmware, and software teams.

Senior level · 10+ years · Full-time

Quick apply — this platform usually takes a CV and a few fields.

Must have (10)
ISO 26262IEC 61508HARAFMEA or FmedaFTADFAECCLockstepBISTRTL
Nice to have (3)
SOTIFISO 21448ISO/SAE 21434

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

How this req sits in the market our data

What gives you an edge
ISO 262622%

Rare in this occupation — lead with these, and say what you built with them.

What the occupation pays Median $119,144 (middle half $81,115–$160,963).

Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.

Why we read it this way (6)

No work location is specified in the posting; the CBSA and state fields are left blank. The role appears to be at an early-stage company (Velaura) with no office address disclosed.

The SOC classification is genuinely difficult. This is a hardware/silicon functional safety architecture role — it does not map cleanly to any standard SOC code. 15-1299 (Computer Occupations, All Other) is used as the best available fit; 15-1252 (Software Developers) is the runner-up given the cross-cutting firmware and platform software scope, but the primary work is silicon safety architecture rather than software development.

The degree requirement states 'Bachelor's or advanced degree… or equivalent practical experience.' Because equivalent experience is explicitly accepted, no formal degree is treated as a hard gate.

DFMEA and FMEDA are listed alongside FMEA in the posting; FMEDA is captured as an alternative to FMEA since they serve the same analytical function in this context. DFMEA is a variant of FMEA and is subsumed.

Functional Safety Engineer certification (e.g., TÜV credential) is listed under Preferred Qualifications and is not treated as a hard gate.

No compensation figures are provided in the posting.

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