Hardware Engineer (FPGA/ASIC) at Jane Street
New York, NY
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Jul 13, 2026
New York, NY
Jul 21, 2026
What this job asks for AI summary
A hardware engineering internship focused on using OCaml and Hardcaml — an OCaml-based RTL library — to design, test, and validate FPGA or ASIC hardware. Interns take a single project from concept to working design, with close mentorship from full-time engineers. The role suits candidates with hands-on HDL experience (e.g. Verilog, VHDL) and familiarity with FPGA or ASIC vendor toolchains.
Junior level · New York-Newark-Jersey City, NY-NJ-PA · Internship
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 250 people in the New York-Newark-Jersey City, NY-NJ-PA area plausibly meet what this posting asks for (software developers). range 110–550
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $170,499 (middle half $133,523–$210,499).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
This is a student internship role; seniority is set to Junior accordingly. No overall years-of-experience requirement is stated.
OCaml and Hardcaml are explicitly called out as NOT required upfront ('No previous knowledge of Hardcaml is required'; 'We don't expect you to have a background in … OCaml, functional programming') — they appear as learning outcomes and stack context rather than gates, so they are marked preferred.
The HDL requirement (VHDL, Verilog, Chisel, Pymtl, 'or other') is listed under the 'About You' requirements block with firm language ('Experienced with'); VHDL is used as the primary name with the others as named alternatives.
Vendor tooling (Vivado/Quartus for FPGAs, Genus/Innovus for ASICs) is similarly gated in the 'About You' block; all four are captured as alternatives under a single skill since the JD treats them as interchangeable platform options.
SOC confidence is Medium: the role is primarily hardware RTL design (FPGA/ASIC), which sits at the boundary of software development (15-1252, via Hardcaml/OCaml) and hardware/systems engineering. 15-1244 is noted as a runner-up, though the emphasis on writing RTL code and software tooling leans toward 15-1252.
Location is inferred as New York (Jane Street's primary office); the posting does not explicitly state a city but Jane Street is headquartered in New York, NY.
Posting is for a internship engagement — the market benchmarks below price full-time roles, so read the comp comparison with that in mind.
Read the full posting
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