Lead ASIC Digital Design Engineer at General Dynamics Mission Systems, Inc
Annapolis Junction, MD
$176,512–$187,000from the description
Jul 27, 2026
Annapolis Junction, MD
Jul 29, 2026
What this job asks for AI summary
A hands-on RTL design lead role at General Dynamics Mission Systems focused on the full ASIC/FPGA design lifecycle — from microarchitecture and RTL coding through synthesis, timing closure, and physical verification. The engineer will own design quality, lead code reviews and verification efforts, and contribute to program planning and proposals. Best suited to an experienced digital hardware designer with ASIC tape-out exposure and comfort working independently on complex, defense-oriented programs.
Senior level · 8+ years · Full-time
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We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (7)
This is an ASIC/FPGA digital hardware design role — not a software development role in the conventional sense. None of the available SOC codes precisely cover ASIC/digital hardware design engineers; 15-1299 (Computer Occupations, All Other) is the closest available fit. 15-1252 (Software Developers) is listed as the runner-up because BLS sometimes classifies embedded/hardware-adjacent digital design work there, but it is a poor match for RTL/ASIC work.
No work location is specified in the posting beyond General Dynamics Mission Systems being a US defense contractor; the CBSA and state fields are left blank accordingly.
The title 'Lead' is treated as equivalent to 'Senior' for advertised seniority purposes; the 8–12+ year requirement and scope of ownership support a Senior classification rather than Staff or Principal, as the role appears to be a technical lead within a team rather than an org-wide authority.
FinFET process node experience (7nm, 5nm) is explicitly called 'a meaningful differentiator' rather than a hard requirement, so it is marked preferred.
Commercial foundry flow experience (TSMC, GlobalFoundries, Samsung) appears in the requirements section but is framed as 'or equivalent,' so TSMC is listed as the primary skill with the others as alternatives.
No security clearance is explicitly required in this posting, though the defense context (General Dynamics Mission Systems) makes one likely in practice; candidates should verify directly.
Ignored 6 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, ASIC design, FPGA design, Bus fabric design, Static timing analysis (STA), Power analysis.
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