Senior ASIC Digital Design Engineer at General Dynamics Mission Systems, Inc
Annapolis Junction, MD
$142,166–$150,000from the description
Jul 26, 2026
Annapolis Junction, MD
Jul 29, 2026
What this job asks for AI summary
An ASIC design engineering role at General Dynamics Mission Systems focused on RTL design within a structured, defense-oriented team. The engineer will own RTL development tasks, contribute to timing closure, support formal verification processes alongside a dedicated verification team, and participate in code reviews and program planning. Suited to someone with 5–8+ years of ASIC/FPGA design experience who has worked in larger, process-driven design environments.
Senior level · 5+ years · Bachelor's required · Secret clearance · Full-time
Long application — this platform typically asks you to create an account and re-enter your work history.
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 29, 2026. It is a model, not a headcount.
Why we read it this way (9)
Job location is not specified in the posting; no CBSA or state could be determined. General Dynamics Mission Systems has facilities across the US — hiring managers should confirm the work site.
The title 'Advanced ASIC Design Engineer' carries no standard seniority level word; advertised seniority is treated as Unspecified. The 5–8+ years requirement and structured-team ownership scope support a Senior classification.
Clearance requirement is stated as 'ability to obtain' a Secret clearance — not an active clearance in hand — but it is explicitly required at time of hire and gates the role.
A Bachelor's degree in Electrical/Computer Engineering or a related STEM field is hard-required; a Master's plus 3 years is offered as an alternative path, but the minimum formal degree gate is a Bachelor's.
FinFET process node familiarity (7nm, 5nm) is described as 'a differentiator' and commercial foundry flow familiarity is framed as contextual knowledge rather than a hard gate — both marked preferred.
ASIC tape-out experience is explicitly called 'a plus' — marked preferred.
The SOC code 15-1252 (Software Developers) is the closest available match for hardware RTL/ASIC design engineering; 15-1299 (Computer Occupations, All Other) is noted as a runner-up. BLS does not have a dedicated ASIC/hardware design SOC in this list.
Ignored 7 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, ASIC design, FPGA design, static timing analysis, clock domain crossing analysis, bus fabric design, power analysis.
Requires a Secret clearance — the cleared population is a small fraction of this occupation, so the real candidate pool is materially smaller than the estimate below, which does not model clearance.
Read the full posting
The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.