Maania Consultancy Services · TX

Salary
Posted
Jul 5, 2026
Location
TX
Last confirmed open
Jul 21, 2026

What this job asks for AI summary

This role centers on FPGA design and verification, with day-to-day work spanning RTL development in VHDL/Verilog/SystemVerilog, testbench creation, and UVM-based verification. The position also involves working with FPGA design flows — including simulation, synthesis, and Libero SoC tools — and integrating FPGAs with Linux or RTOS environments. It suits an engineer with a solid background in digital design principles and real-time embedded systems.

Mid level · 3+ years · Austin-Round Rock-Georgetown, TX · Bachelor's required · Full-time

Must have (6)
VHDL, Verilog or SystemverilogUVMModelSimLibero SoCAXI or AvalonLinux or Rtos

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

How this req sits in the market our data

Roughly 40 people in the Austin-Round Rock-Georgetown, TX area plausibly meet what this posting asks for (software developers). range 8–60

Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.

What gives you an edge
UVM1%VHDL3%

Rare in this occupation — lead with these, and say what you built with them.

What won't set you apart
Linux45%

Most people in this occupation already list these. Still required — just not what gets you shortlisted.

What the occupation pays Median $137,069 (middle half $106,287–$172,440).

Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.

Why we read it this way (6)

The role title is 'Embedded Firmware Engineer – FPGA Development'; no seniority level appears in the title, so advertised seniority is Unspecified. The 3–5 year experience range and scope of work support a Mid-level classification.

SOC classification is Medium confidence: FPGA/RTL firmware work sits at the boundary between Software Developers (15-1252) and the catch-all Computer Occupations (15-1299); the primary deliverable is synthesizable hardware description code rather than traditional software, but 15-1252 is the closest standard code.

The degree requirement states 'Bachelor's or Master's degree' — Bachelor's is treated as the minimum hard requirement.

The posting is from a staffing/recruiting firm ('our client is looking for…') and asks for expected salary rather than quoting a range; no compensation figures are provided.

Only U.S. citizens or permanent residents are eligible, per the posting.

Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, FPGA design.

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