Dallas, TX

Salary
$150,000–$230,000
Posted
Jul 27, 2026
Location
Dallas, TX
Last confirmed open
Sep 24, 2026

What this job asks for AI summary

An FPGA Design Engineer role at a defense-tech company focused on UAV autonomy systems. The engineer will design, implement, verify, and debug FPGA-based digital communication and timing modules for avionics platforms, working closely with hardware, firmware, and software teams through board bring-up, timing closure, and system integration. Suits a candidate with strong digital design fundamentals and hands-on AMD/Xilinx experience.

Senior level · San Diego, CA · Bachelor's required · Full-time

Pay in the description: $150,000–$230,000

Quick apply — this platform usually takes a CV and a few fields.

Must have (4)
VHDL or Systemverilogtiming closureclock domain crossingGit
Nice to have (6)
VivadoEthernetAXI4AXI-StreamTCLCI/CD

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

How this req sits in the market our data

Roughly 100 people in the San Diego, CA area plausibly meet what this posting asks for (software developers). range 30–150

Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.

What gives you an edge
VHDL3%

Rare in this occupation — lead with these, and say what you built with them.

What the occupation pays Median $166,860 (middle half $131,418–$198,246). This posting is about at that midpoint.

Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 1, 2026. It is a model, not a headcount.

Why we read it this way (6)

The posting does not specify a single work location beyond Shield AI's broad U.S. presence; San Diego, CA is used as the CBSA because that is Shield AI's primary headquarters city.

SOC classification is Medium confidence: FPGA design sits at the boundary between hardware engineering (not in the SOC list) and software/digital design (15-1252). The role primarily involves writing and verifying RTL code and building digital systems, which maps most closely to Software Developers; 15-1299 (Computer Occupations, All Other) is the runner-up.

VHDL and SystemVerilog are listed together as interchangeable options ('VHDL or SystemVerilog') in the required qualifications; they are captured as a single skill with alternatives.

Git is listed under required qualifications with 'familiarity with version control tools such as Git' — the 'such as' qualifier means Git is interchangeable, but the version-control capability itself is a hard gate.

A background check is required per the posting; no active security clearance is gated.

Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): FPGA design.

Read the full posting

The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.

Apply

Apply on employer site ↗