Hardware/Software Design Engineer 3 at Wyetech
Annapolis Junction, MD
$153,795–$208,270
Jul 12, 2026
Annapolis Junction, MD
Jul 21, 2026
What this job asks for AI summary
A senior engineering role focused on designing and developing FPGA-based hardware and software components for RF communication and collection subsystems serving federal government customers. Day-to-day work centers on implementing DSP algorithms in FPGA RTL, achieving timing closure, integrating FPGA designs with Linux-based software stacks in C/C++, and documenting technical efforts. Suited to an experienced FPGA/DSP engineer holding an active TS/SCI clearance with a relevant polygraph.
Senior level · 8+ years · Baltimore-Columbia-Towson, MD · TS/SCI clearance · Full-time
Pay in the description: $73.94–$100.13/hr
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $141,954 (middle half $107,994–$205,328). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (6)
The role is a genuine HW/SW hybrid — primary day-to-day work spans FPGA RTL development (hardware) and software integration (C/C++, Linux); 15-1252 Software Developers was chosen because the JD emphasizes writing and shipping code (RTL, integration code, system-level software) rather than operating existing infrastructure. 15-1299 (Computer Occupations, All Other) is a reasonable runner-up given the embedded/hardware-engineering character of the work.
Degree requirement: the JD states 'Bachelor's degree plus 8 years of relevant experience OR equivalent,' meaning equivalent experience is explicitly accepted in lieu of a degree — the degree requirement is therefore None.
Clearance: the JD hard-gates on an active TS/SCI with agency-appropriate polygraph.
Vivado is listed under 'Desired Technical Skills' with the word 'required' in an unusual phrasing ('Additional experience with Vivado required'). However, it appears in the desired/preferred section alongside the explicitly preferred Epiq Solutions PDK, so it is treated as preferred rather than a hard gate. Hiring managers should note this ambiguity.
Work locations span Maryland, Virginia, Colorado, Texas, Utah, Alaska, Hawaii, and OCONUS; the CBSA is set to Baltimore-Columbia-Towson, MD as the company's primary base, but the actual assignment location may differ.
Requires a TS/SCI clearance — the cleared population is a small fraction of this occupation, so the real candidate pool is materially smaller than the estimate below, which does not model clearance.
Read the full posting
The employer publishes the full description on their own site — read it there ↗. Or sign in to read it here — it's free, and it also lets you track this application.