Remote | ASIC/SoC Hardware Design & Verification Engineer — $65–$95/hour at 24-MAG
New York, NY
$65–$95/hrfrom the description
Jul 19, 2026
New York, NY
Jul 20, 2026
What this job asks for AI summary
A part-time, fully remote contract role for US-based semiconductor engineers to support an AI training initiative. Work involves creating realistic ASIC and SoC engineering problems, writing reference RTL solutions in SystemVerilog or Verilog, and evaluating AI-generated hardware designs for correctness and quality. Suits practitioners with hands-on chip design, verification, or tapeout experience who can commit roughly 20–40 hours per week.
Senior level · Remote · Contract
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 730 people nationally plausibly meet what this posting asks for (computer occupations, all other). range 310–1,100
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $119,144 (middle half $81,115–$160,963). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (11)
This role is a part-time W-2 contract (described as 'W-2 contingent employment') at 20–40 hours/week — classified as Contract given its contingent, project-based nature.
The primary occupation is ASIC/SoC hardware engineering (RTL design, verification, tapeout), which does not map cleanly to any standard software-developer SOC. 15-1299 (Computer Occupations, All Other) is the best fit; 15-1252 (Software Developers) is the runner-up given the RTL coding and testbench-writing duties.
SystemVerilog and Verilog are listed as required ('strong fluency in SystemVerilog, Verilog, or both') but are explicitly interchangeable — emitted as two separate skills each listing the other as an alternative, reflecting that either alone satisfies the requirement.
RTL design and functional verification are treated as hard gates: the posting's 'Ideal Profile' section uses firm language ('hands-on experience in ASIC or SoC design, functional verification…') and the role's core deliverables depend on them.
A degree is described as 'highly relevant' and 'equivalent hands-on engineering experience may also be considered' — not a hard gate, so the degree requirement is set to None.
All 'Nice to Have' skills (UVM, SVA, CocoTB, formal verification, specific EDA tools, open-source tools, protocol experience) are marked preferred per the explicit section heading.
No overall years-of-experience floor is stated numerically; seniority is assessed as Senior based on the expectation of production silicon / tapeout experience and independent work on complex design problems.
The posting is placed through 24-MAG LLC, a staffing intermediary — the end client is described only as an 'advanced AI initiative.'
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design.
Posting is for a contract engagement — the market benchmarks below price full-time roles, so read the comp comparison with that in mind.
Caller marked this a fully-remote role — scored against the national candidate pool.
Read the full posting
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