Staff Mixed-Signal Verification Engineer at Renesas Electronics
Chandler, AZ
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Jul 20, 2026
Chandler, AZ
Jul 23, 2026
What this job asks for AI summary
This role centers on chip-level verification and behavioral modeling of mixed-signal power management devices, such as PMICs and battery chargers. Day-to-day work involves building and maintaining circuit models in SystemVerilog and Verilog-AMS, developing verification plans, debugging simulation failures, and coordinating with design and systems teams. It suits an experienced mixed-signal or digital verification engineer with a background in semiconductor development and power management.
Senior level · 8+ years · Bachelor's required · Full-time
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $119,144 (middle half $81,115–$160,963).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (5)
No work location is specified in the posting; CBSA and state fields are left blank. The role is at Renesas Electronics, a global company, but the posting does not name a city or country — it defaults to US-based given the export-control language referencing U.S. regulations.
This role sits at the intersection of hardware/EE and software verification. No standard SOC code cleanly covers mixed-signal/analog IC verification engineering; 15-1299 (Computer Occupations, All Other) is the closest fit, with 15-1252 (Software Developers) as a runner-up given the modeling and simulation coding work in SystemVerilog and Verilog-AMS.
The JD lists 'mixed-signal verification, digital verification, modeling, power management, or related semiconductor development' as a single compound experience requirement — these are domain descriptors rather than discrete named tools, so only the concrete languages (SystemVerilog, Verilog-AMS) are captured as skills. Switching converter experience is explicitly called a plus (preferred), but names no specific tool.
The degree requirement is B.S. or M.S.; B.S. is the minimum hard gate and is captured accordingly.
No compensation figures are provided; the posting states details will be shared during the hiring process.
Read the full posting
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