Digital Verification Engineer at Nexthop Systems Inc
Santa Clara, CA
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Jul 21, 2026
Santa Clara, CA
Jul 22, 2026
What this job asks for AI summary
This role centers on building and maintaining verification environments — testbenches, drivers, monitors, scoreboards, and regression suites — for digital subsystems targeting both FPGA and ASIC designs. Day-to-day work spans writing constrained-random and directed tests, closing functional and code coverage, debugging simulations in Modelsim/Questasim or NC-Verilog, and supporting lab bring-up alongside RTL and firmware engineers. It suits someone with 3–7 years of hands-on digital verification experience and solid SystemVerilog skills.
Mid level · 3+ years · San Jose-Sunnyvale-Santa Clara, CA · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
What the occupation pays Median $170,192 (middle half $126,400–$188,281).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 29, 2026. It is a model, not a headcount.
Why we read it this way (10)
The title carries no seniority level word; advertised seniority is Unspecified. The 3–7 year experience range and scope (block-level through subsystem integration, no people-management) map to a Mid-level role.
The JD states 'BS/MS in Electrical Engineering, Computer Engineering, or a related field' as a required qualification. Because a Bachelor's is the minimum of that range and no equivalent-experience substitution is offered, the degree requirement is set to Bachelors.
Verilog is listed as the required language with SystemVerilog 'strongly preferred'; SystemVerilog is captured as the primary skill with Verilog as an alternative, reflecting that either satisfies the gate.
Modelsim/Questasim and NC-Verilog are listed together under required tools as interchangeable simulators; Modelsim is the primary name with Questasim and NC-Verilog as alternatives.
SVA (SystemVerilog Assertions) is called out explicitly in the required methodology section and treated as a hard gate.
UVM appears only under 'Strong Pluses' and is therefore preferred.
RTL design knowledge and HW/SW co-validation experience appear under 'Strong Pluses'; they are preferred, not required.
Networking/switching datapath and high-speed interface familiarity are mentioned under 'Strong Pluses' but name no specific concrete technology, so they are omitted per the generic-concept rule.
This role is primarily hardware/digital verification (testbench authoring, simulation, coverage closure) rather than traditional software QA; 15-1253 is the closest SOC match, with 15-1252 as a reasonable runner-up given the significant code-authoring component.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design.
Read the full posting
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