Performance Verification Engineer at DensityAI
Mountain View, CA
$200,000–$350,000
Jul 25, 2026
Mountain View, CA
Jul 26, 2026
What this job asks for AI summary
This role centers on performance verification and correlation at both the block and SOC level for an AI accelerator chip, spanning from initial silicon bring-up through scaled deployment. The work involves building and running performance tests, debugging discrepancies between performance models and RTL, and collaborating with hardware architects and software teams. It suits an experienced engineer with a strong background in complex SOC performance validation and industry-standard tracing and compilation toolflows.
Senior level · 8+ years · San Jose-Sunnyvale-Santa Clara, CA · Master's required · Full-time
Pay in the description: $200,000–$350,000
We read this from the posting text with AI. Skim the description below before ruling yourself out.
Why we read it this way (7)
The role is primarily hardware/silicon performance verification and correlation on AI accelerator SOCs — it sits at the boundary of hardware validation (15-1253) and silicon/software co-development (15-1252). 15-1253 was chosen because the core deliverable is verification and debug, not shipping production software.
The JD requires 'Master's + 8 years'; the degree gate is a Master's (or higher implied), and 8 years is the stated experience floor tied to performance validation/verification on complex SOCs.
No specific named tools are called out beyond generic references to 'industry-standard tools for tracing, compilation and related workflows' — no concrete tool names (e.g. Synopsys, Cadence, VCS, Verdi, gem5) are given, so skills are captured at the capability level rather than as named products.
Processor verification, compiler exposure, and hardware validation are explicitly marked '(Optional)' in the JD and are listed as preferred.
The California pay range ($200,000–$350,000/year) is the only compensation figure provided; the posting notes final offers depend on level, location, and skills.
Location is inferred as California (Silicon Valley area) based on the California pay range and the nature of the AI accelerator chip-design role; no specific city is stated.
Ignored 1 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): performance modeling.
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