Mountain View, CA

Salary
$180,000–$320,000
Posted
Jul 25, 2026
Location
Mountain View, CA
Last confirmed open
Jul 26, 2026

What this job asks for AI summary

A hardware verification engineering role focused on the compute core of an AI accelerator ASIC, covering tensor pipelines, MAC arrays, accumulator logic, and the compute-to-memory interconnect. Day-to-day work involves SystemVerilog/UVM-based constrained-random and coverage-driven verification, numerical correctness validation, and developing AI-assisted tool flows to speed up datapath verification. Suited to engineers with substantial experience verifying compute-intensive blocks such as GPUs, NPUs, or similar accelerators.

Senior level · 5+ years · Full-time

Pay in the description: $180,000–$320,000

Must have (4)
SystemVerilogUVMconstrained-random verificationcoverage-driven verification
Nice to have (3)
formal methodsC or C++Python

“or” means any one of them counts — you don't need all of them.

We read this from the posting text with AI. Skim the description below before ruling yourself out.

How this req sits in the market our data

Roughly 20 people in CA plausibly meet what this posting asks for (software quality assurance analysts and testers). range 6–30

Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.

What gives you an edge
UVM1%SystemVerilog2%

Rare in this occupation — lead with these, and say what you built with them.

What the occupation pays Median $131,571 (middle half $95,587–$169,170). This posting is about at that midpoint.

Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.

Why we read it this way (6)

The job title is not stated in the posting; the role is inferred as a hardware/ASIC verification engineer based on the described responsibilities (datapath verification, tensor pipelines, MAC arrays, UVM testbenches).

SOC 15-1253 (Software QA Analysts and Testers) is the closest available code for hardware verification engineering; 15-1252 (Software Developers) is a plausible runner-up given the custom golden-model and tool-flow development aspects.

The compensation range ($180,000–$320,000/year) is explicitly labeled as a California pay range; the posting does not specify a city or CBSA, so the metro field is left blank.

The posting notes the role 'may involve access to information subject to U.S. export controls (EAR/ITAR)' but does not gate on a security clearance — no clearance is required.

Formal methods, C/C++ golden models, Python, and ML-framework familiarity are listed under an explicit '(Optional)' bullet and are marked as preferred accordingly.

The wide compensation band ($180K–$320K) reflects the posting's note that 'final offers depend on level' — the role may be filled at multiple seniority levels.

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