Design Verification Engineer - DDR Memory Subsystem at Microsoft
Raleigh, NC
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Aug 16, 2026
Raleigh, NC
Sep 25, 2026
What this job asks for AI summary
This is a hardware verification engineering role focused on Memory Controller IP and subsystem verification. The engineer will define verification strategies, build UVM-based and formal verification environments, and apply coverage-driven and random-stimulus techniques to validate designs involving protocols such as CHI, AMBA, and JEDEC. The role also involves mentoring peers and applying generative AI tooling to verification workflows.
Mid level · 2+ years · Bachelor's required · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $138,970 (middle half $107,524–$175,762).
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Aug 18, 2026. It is a model, not a headcount.
Why we read it this way (4)
The posting presents two distinct experience tiers. The minimum (likely the base/hiring bar) requires a Bachelor's + 2 years or Master's + 1 year; a higher preferred tier requires a Bachelor's + 5 years, Master's + 3 years, or a Doctorate. The overall years minimum is set to 2 (the minimum gate); the higher tier is treated as preferred.
UVM, SystemVerilog (SVTB), Formal Verification, and Python are listed in the preferred/senior qualifications block but are the core technical substance of the role — they appear with firm, demonstrated-experience language ('Experience creating, maintaining, or integrating test benches… using UVM, SVTB, formal test bench'). They are marked required as they represent the primary technical gates of the role.
CHI, AMBA, JEDEC, PCIe, and CXL protocol knowledge, along with Generative AI experience, appear in the preferred qualifications block and are marked accordingly.
The posting includes an export-control citizenship/residency verification requirement as a condition of employment, which may restrict candidates who are not US citizens, lawful permanent residents, refugees, or asylees.
Read the full posting
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