Senior Technical Program Manager - AI Acceleration
NVIDIA Corporation · Santa Clara, CA
$168,000–$322,000from the description
Jun 30, 2026
Santa Clara, CA
Jul 21, 2026
What this job asks for AI summary
A senior program management role focused on bringing AI capabilities into chip design and hardware development workflows. The position involves coordinating across ASIC engineering, internal AI platform teams, and third-party tool providers — overseeing planning, adoption, and delivery of AI tools such as agents and LLM-powered systems. Suited to someone with deep experience in both technical program management and silicon design processes.
Senior level · 10+ years · Santa Clara, CA · Full-time
“or” means any one of them counts — you don't need all of them.
Posted 2 times — it's one opening, so apply once.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
What the occupation pays Median $188,486 (middle half $139,113–$224,920). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
The role is a Technical Program Manager, not a pure engineering IC or people manager — 15-1299 (Computer Occupations, All Other) is the best fit for a senior TPM in a technical domain; 11-3021 is a plausible runner-up given the leadership and cross-org scope.
The posting covers two salary bands (Level 4: $168,000–$258,750; Level 5: $200,000–$322,000). The min and max reported here span both bands combined ($168,000–$322,000), as the specific level for this hire is unspecified.
Location is not explicitly stated in the posting; NVIDIA's headquarters in Santa Clara, CA is used as the default CBSA. The note about cross-geography coordination suggests the role may span multiple sites.
Degree requirement is marked None because the JD explicitly accepts 'equivalent experience' in lieu of a Bachelor's degree.
RTL design, simulation, formal verification, and ASIC chip design are listed under the hard-requirements block ('What we need to see') and are treated as gates even though they describe domain knowledge rather than discrete tools.
Cloud infrastructure, orchestration systems, and data pipelines appear only under 'Ways to stand out from the crowd' (the preferred/nice-to-have section) and are therefore not hard gates.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, ASIC chip design.
Read the full posting
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