Senior ASIC Hardware Design Engineer
NVIDIA Corporation · Westford, MA
$136,000–$264,500from the description
Jul 1, 2026
Westford, MA
Jul 21, 2026
What this job asks for AI summary
This role sits within the NVLink ASIC Design team, focused on designing chip-to-chip communication and GPU interconnect subsystems. Day-to-day work involves micro-architecture development, RTL implementation and debugging, timing closure, and supporting physical design activities such as floor planning and power analysis. It suits engineers with hands-on experience in complex digital design using Verilog or SystemVerilog.
Mid level · 5+ years · Santa Clara, CA · Bachelor's required · Full-time
“or” means any one of them counts — you don't need all of them.
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Roughly 650 people in the Santa Clara, CA area plausibly meet what this posting asks for (software developers). range 340–850
Applicant volume Moderate — A normal amount of company. The rare requirements below are what will separate a shortlisted application from the rest.
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $217,796 (middle half $177,469–$231,052). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
This is a hardware/ASIC design role (RTL, Verilog/SystemVerilog, VLSI, synthesis/timing closure) — not a traditional software development role. SOC 15-1252 is the closest available code; 15-1299 (Computer Occupations, All Other) is a reasonable runner-up given the specialized hardware engineering nature of the work.
The posting covers two internal levels (Level 3: $136,000–$218,500; Level 4: $168,000–$264,500). The compensation range above spans both levels combined. The seniority band reflects the 5+ years minimum requirement, which maps to Mid-to-Senior; given the two-level span and the lower bound of 5 years, Mid is chosen as the conservative estimate.
Location is not explicitly stated in the posting; NVIDIA's NVLink ASIC team is headquartered in Santa Clara, CA — the CBSA reflects that inference.
Degree requirement: the JD states 'Bachelor's or Master's degree … or equivalent experience.' Because equivalent experience is explicitly accepted, the degree field is set to None per extraction rules — however, the posting does name a degree as the primary credential.
'Low-power build methodologies' and 'high-speed build methodologies' appear under the 'Ways to stand out from the crowd' section, marking them as preferred/nice-to-have.
Scripting language requirement lists Perl or Python as interchangeable; Python is used as the primary name with Perl as the alternative.
Ignored 3 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, low-power design, high-speed design.
Read the full posting
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