AI/ML Logic Design Engineer-Senior at Qualcomm
Austin, TX
$127,200–$190,800from the description
Jul 14, 2026
Austin, TX
Jul 21, 2026
What this job asks for AI summary
This role centers on designing the microarchitecture and RTL for Qualcomm's Hexagon neural processing unit, targeting AI and machine learning workloads. Day-to-day work spans SystemVerilog RTL development, early logic synthesis, static timing analysis, and power estimation, carrying features from initial concept through tape-out. It suits engineers with a background in high-performance microprocessor design who are comfortable working across architecture, implementation, and EDA tooling.
Mid level · 2+ years · National · Bachelor's required · Full-time
We read this from the posting text with AI. Skim the description below before ruling yourself out.
How this req sits in the market our data
Rare in this occupation — lead with these, and say what you built with them.
Most people in this occupation already list these. Still required — just not what gets you shortlisted.
What the occupation pays Median $138,970 (middle half $107,524–$175,762). This posting is about at that midpoint.
Estimated from BLS employment for this occupation and area, per-skill prevalence across our listing corpus, and published wage benchmarks — as of Jul 28, 2026. It is a model, not a headcount.
Why we read it this way (7)
The role is primarily hardware/microarchitecture (NPU RTL design, logic synthesis, STA, PPA analysis) rather than traditional software development. SOC 15-1252 (Software Developers) is the closest available code given the RTL/design-automation coding emphasis; 15-1299 (Computer Occupations, All Other) is a reasonable runner-up for this hardware-engineering profile.
No work location or CBSA is specified in the posting. Qualcomm's primary US engineering hub is San Diego, CA, but this cannot be confirmed from the text alone.
The minimum qualification allows a Bachelor's + 2 years, a Master's + 1 year, or a PhD with no experience — 'Bachelors' is set as the minimum formal degree since the PhD path requires no stated experience and the Master's path requires only 1 year, but a Bachelor's is the lowest-tier entry point explicitly listed.
The 'Required Skills & Qualifications' section lists AI/ML concepts as a solid foundation requirement, treated as a hard gate per its placement in the required section.
'RTL design' is listed as a named methodology/discipline that is central to the role's day-to-day work and explicitly required; retained as a skill despite being somewhat methodological because it is the core technical deliverable of the role.
Total years minimum is set to 2, reflecting the '2+ years of experience with high-performance microprocessor design' stated under Minimum Qualifications — the most specific role-level experience gate in the posting.
Ignored 2 non-technology phrase(s) as skills (responsibilities/concepts, not named tools): RTL design, static timing analysis.
Read the full posting
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